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Page2
ABSOLUTE MAXIMUM RATINGS <
SYMBOL PARAMETER RATING UNIT
VOC
TA
Ti
TSTG
Supply voftage
operating free air arnbient temperature range
Junction temperature
Storage ltemperature range
Maximum power dissipation
6
0 to + 70
+150
-65 to +150
500
V
°C
°C
°C
mW
ELECTRICAL
CHARACTERISTICS

The electrical characteristics listed below are actual tests (unless otherwise stated) per-

formed on each device with an automatic IC tester prior to shipment. Performance of the device In automated test setup Is not necessarily optimum. The NE568 is lay-out sensitive..

EVMAlJDn Of PWWff*nC* fOr OWWROOn tO Vw4ft ~ - -Mbe dmWwNh dw drewt wW Wjwt of FOAU l - 3 whh the ev"tion ur* wkJsW in plem (Do not use a sockatf)

DC ELECTRICAL CHARACTERISTICS TA - 25*C, Voc - 5VL to - 70MH4 Test Circuit FigLw* 1. fIN - -20dSm, -011 (gmnd). unkm oVwvAse specWled. SYMOM VOC IOC PARAMETER Supply VORMOS Sw* wfent TEffr CONDnxm mm 4.75 U&M T" mox 5 525 w l 76 UNIT v ffkA f%UAnAd%'rCOlOVle4-' l TEST CONDITHM uw to tosc ow RIN 10 fo Maxkmm owMator operating trequency lrqxd sow lovel Doomdulated bandwkIth Nor,kmvity5 Lock. Capt wo rang*2 TC of fo IrPA remostarloo OuW Wnpodame DWnO"tOd VOUT AM r*ctlon Dift with supply -E Dev 2o%, Ir4m - -2DdBm Input - - 2OdBm Input - -2DdBm Figure l Dev - 20% of fo nmmwjred st Pln 14 VIN - -2DdBm (30% AM) reforred to 20% devistion Cente(ed st 70MHz. A2 - 1 2kil. G2 - 17pF, R4 - On (C2 + CSTRAY - 2OPF) 4.75V to 6.25V wn 150 50 -20 t25 20 1 0.40 -15 TYP fo/7 1.0 t 35 t3o i0o a 0.52 So 0 1 moz 2000 + 10 4.0 + 15 MHz MVP.P dBm MHZ % of fo % of fo ppm/'C kn vp-p dB NOTM 1. Sow level to o"We @M pAAshod porwratem Device wiN oonWp-e to hwwbon st kmw Wmis with wOW pw*wnwm. 2. Un*s we W Ww*Mwl lo to. AftW chigracWsbm may have asymme" boyand the Wwifted Nnta. 3. Not 100% lodecL IxA gkwant@W by ~. 4. ln;Kg Woft*M 1 ; ' on pakW Wd WMA eWaq-. Ses Fom 4 " 5. Lwwaft is Now Whh woomm" dumn in WPA froWency WW MOOMMYWR of tho C)C vApA v~ st Pin 14 (VOUT), Nw*mrdy is then cakulaw from s dftUlbon mngo VedfWd- 5. Ffoo-rurnng tro".=,.y foodilvough to Pin M (VOUT) whh no bpA 9WW appkd. Page3 .,,*.CtMAL DESCRIPTION tv NEW is a high-perforawknoe ph (PLL). The circuit consists of PLL elempents, with speciol cirPft-for Oneartzed demodulated output, and WkIfewer" perf- The process ifta has NM tranalstors with fT > 6GHz. ~P*ho Own V4 bandwidth of these trAnsms 4 LM,afte careM attention to layout and ,"M critcal for optirnum performance. The LL connot be evaluated ayout. The use of the this deta sheet wW tora wo hq* recornas a starting point. MO kVtfi to the PLL Is through a lirniting *-Ww WAh a gain of 200, The input of thm _I!bPMW, le differential (Pins l 0 and 11). For .f4b,fflded applicatiorm the irPA must be *498d. through a DC-blockmv capacitor with AW OpWanc* at the frequency of Interest. *4"nded W4xd is normaMy applied to 11 with Pln l 0 AC-bypessed with a low,hipadar" cWwtor. The kqPA 009dence Is .010fuctOrMcalty slightly above SQOQ Imped.mrV* Matoh W not neoessary, W loaft the ftW SOWCO should be avolded. When the SOUMWII 50 or 75A a DC-blocking capacitor WUSNY ER that w needed. Aim-mmmicatig. is WO am-h tQ o---" ,A"irrhlince of the P morpaxwt of the l *'Pim'. W,-A i. vw~ capeci NOWN WX in the case of large eno* for good AM rejec- ampiftation. the inpirt signel port of a nwhiplier-cell ~ other port l* drtv*n by the led oscillator (0)). The Wqkd oomparstor l$ A voltage propor- ,10 the phame difference of the OW mW 19" S.gnW fi;~KOW Wft~ a lCO signals. The Orrm low-pass fifter to provide a DC-coffection voltage, and thia voltage is converted to a current which a applied to the W, shifting the frequency in the dmW which causes the input and K)O to have a 90* phase relationshp. The o6cMator is a owrort-con"Ned mumvil). rator. The current control affects the charge/ discharge rate ~f the tirni4g capacitor. It la common for this type of oscillator to be referred to as a vottage-controlled oscillator (VCO), because the output of the phase comparstor and the loop Mer is * voltage. To control the frequency of an integrated ICO mLdUv&ator. the control sgnal rnust be conditioned by a vottage-tG-mvent converter. In the NE568, spectal circuitry predlatorts the control 99W to make the change in frequency a WxW kuxim over a large conVo4voltage range. The free-running trequency of the oscillalo' depends on the vskis of the Urning capacitor connected between Flins 4 and S., The value of the bn*V capacitor depends on internal reslative components and current sources. When R2 - 1.2kil and R4 - Oft a very close approxombon of the correct capacitor value IS: 0.0014 - F fo C* - 02 -+ CSTRAY- The ternpershins-corriponsation reelstor. R4, affects the ackW vakis of capacitance. This swiation me normalized to 7OMHz. Ses Foxe 6 for corT$cbon factors. The lo6p OW dgftmwm the do" ChWacteristics of the loop. In - most PLLs, the phase detector outputs are internally con. mected to the K)O inputs- The NES68 was designed with Ster otrtput to inpfi conneobona from Pins 20 (0 DET) to 17 (100). and Pins 19 (0 DET) to l S OCO) mdemaL This aisows the use of both series and shunt ftp-~ fifter elements. The loop, constants aw KD - 0. l 27V/Radian (Phass Detector Constant) KO - 4.2 X 109 Asdi&m (ICO C*Mtant) V-sec nArml twhag., grialka M tha IgQ. Capacitors 4 Clo. and resistor RI. control !hs treim, of ft 4 c phase detector. Capacitor C'Vo!ftuppresses 70MHz feedthrough by interaction with 100il load resistors intermal to the phase datoctor. 1 Cq --- F 2v (50)(fo) At 70MHz. the calculated value Is 45pF. EnWscal results with the test and application board were irnproved when a SW capacitor was used. The nakwal freq~ for the loop MW l* M byCloandAlAfthem W NoWeivoyalthe loop is 7OMHz and tho full demodtAsted bandwidth is desired, i.o., fsw-fo/7 - l OMHz. and a v" for R l Is chosen, the vakm of Clo cen be caloulal" l Clo - - F 2w Rjfqw page4 150MHz Phase-Locked Loop NE568 PARTS LIST AND LAYOUT 70MHz APPLICATION NE568D C, C21 C2 2 C3 tc-4--- CS C6 C7 C8 C9 clo -C-1-1-- C-12 C13 RI R2 R:,' R 4 R53 RFC,' FtFr-.5 100nF 18pF 34pF 100nF lOOnF 6.8,uF l OOnF 100nF ~()OnF 56pF 560pF 47pF 100nF 1 OOnF 1.2kSl 43R 4.7kf2 50Q 1OPH I0JJ,H 10% -2% t 2% 10% 10% +10% f 10% f 10% 2% t2% -2% 10% t 10% 10% 10% +10% Geramic chip Ceramic chip Ceramic OR chip Ceranvc chip Ceramic chip Tantalum Ceramic chip Ceramic chip Ceramic chip Ceramic chip Geramic chip Ceramic chip Ceramic chip Ceramic chip Trim pot Chip Chip Chip Surface rnounl Surface mount 1206 0805 1206 1206 35V 12D6 1206 1206 0805 or 1206 0805 or 1206 0805- or 1206 1206 1206 l/ow l/ow 1/13W :iw NOTES: ~ "',N1.1 - ?OPF + C~I-l ~ 36PF for lemp-two- componsaft-,d conliquration wilh R4 - 4 7k~.' Fo, lf)SZ el,,p R, - 62fl. R, - 62'2. R, - 15S.1 lo, 15!~ Ppfilahm 4 For tost configuration R4 - OS! (GNO) dnd (12 - I8PV 1, (S! (:hip -%islor5 (lumpe(s) may to %tibstiloilod with -_ (J"gra,mlion of p-forman- For the test circuit, R, was chosen to bO 272 The calculated value of Clo is 59OpF. 56OpF was chosen as a production value. (In actual satelfite receiver applications, improved video with low cafrier/noise has boon observea with a wider loop-fifter barxtwidth.) A typical application of the NE568 is democlulation of FM signals. In this mode of opera tion, a second single-pole filter is available at Pin 15 to minimize high frequency feed through to the output. The roll-off frequenc~ s set by an internal resistor of 3500 1 20*~ arid an external Capacitor from Pin 15 ground. The vaiue of the capacitor is 1 Cil - F 21r (350)fBW Two final components complete the active part of the circuitry. A resistor from Pin 12 ~o ground sets the lemperature stability of !rle circuit, arid a potentiometer from Rn 1,~ tc ground permits fine tuning of the free-runn ng oscillator frequency. The Pin 16 poienticm,~ ter is normally 1.2kQ. Adjusting this resis tance controls current sources which aflev the charge arid discharge rates of the timing capacitor and. thus, the frequency. The va!~e of the temperature stability resistor is chosen from the graph in Figure 6; the respecIl'oe timing capacitor needs to, be changed The final consideration is bypass capacitors for the supply lines. The capacitors should be ceramic chips. preferably surfacp-mourlt types They must be kept ve~y close 10 !~e device. The capacitors from Pins 8 arid l return to V(:(-,, before being bypassed NIM, a separate capacitor to qround Th.s aslufl-,s that no differential loops aro created whic' might cause instability, The layout; for thE test circuits are recommended page5 pARTS LIST AND LAYOUT'70MHz APPLICAfION NLtl*BN C, r C3 C4 cs ce C, CIB clo Clo cil C12 C13 Rl R2 Ft3' R44 R,3 RFC, RFC, l OOnF 17pF 34pF l OOnF IOOnF 6.8,uF IDOnF IOOnF -;WpF 56OpF 47pF 'OOnF l OOnF 27S2 I.A2 43Q 4 7kSl 5m lOpH lOpH t 10% t2% ~2% t 10% ~ 10*16 10% t 10% -10% 2% , 2'. t2% t lool 10% l 0% t 10% l 10% t 10% + 10% Ce(amic chip Ceramic OR chip Ceramic chip Ceramic chip Ceramic chip Tantalum Ceramic OR chip imic chip Ceramic chip Ceramic chip Ceram,c chip Ceramic,PR chip Ceramic,OR chip Ceramic OR chip Carbon Trim pot --~arb.n Carbon Carbon. 50V 50V 0805 50V 50V i5v 50V 50V sov 50V 50V 50V 50V 50V 1/4W '/4W '/4W 1"W l. C2 + CsTFtAy - 20p~ lw tost configuration mth R, - OSI 2 C2 - 34PF ror tempe,at.re componsated configuration "th R4 - 4 AS 1 3. For 50il setup R, - 62f,', R, - 75ft fof 75fl apphcalons 4.'For test config-l~or- R, l (l l ((-.Nl)j and G2 - I*IpF